(CPU) L2 Cache Design Engineer - Micro-Architecture & Coherency Qualcomm

6.0 - 15.0 years

0 Lacs

karnataka

On-site

Join the High-Performance CPU Design Team at Qualcomm India Private Limited! As an L2 Cache Design Engineer, your primary responsibilities will include driving micro-architecture development for L2 cache subsystems, implementing and optimizing cache coherency protocols for multi-core and multi-socket systems, collaborating with cross-functional teams, analyzing and improving performance, power, and area trade-offs for cache structures, and supporting functional and performance verification. **Key Responsibilities:** - Develop micro-architecture specifications for L2 cache and related coherency logic. - Own RTL design and refinement to meet timing, power, and reliability goals. - Work closely...

Posted 2 days ago

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RTL Design Engineer Evnek

10.0 - 12.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Job Role: RTL Design Engineer Experience: 10+yrs Location: Bengaluru Notice Period: 30days max Role Summary We are seeking an experienced RTL Design Engineer to join our team and contribute to the RTL design and development of the signal processing path for Aeva's advanced 4-D Lidar processing chip. In this role, you will design, implement, and integrate key sub-components into both ASIC and FPGA platforms, ensuring performance, efficiency, and robustness. Key Responsibilities Design and develop custom components for the digital signal processing pipeline, including filters, FFTs, control logic, and related modules. Create micro-architecture specifications, write SystemVerilog RTL code, and ...

Posted 1 month ago

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