7 Skill Scripting Jobs

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a profound knowledge of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and automation of schematic/layout tools. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and robust automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will also be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design environment tasks. Additionally, you will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. A key aspect of the role involves working extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data such as schematic, layout, connectivity, and library information. You will develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist in design data migration or QA. Troubleshooting issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups will also be part of your responsibilities. Moreover, you will document technical processes, create reusable automation scripts, and contribute to team best practices. Collaboration with AI and software teams to integrate EDA tools into the AI co-pilot platform and support the continuous improvement of design automation is essential. The ideal candidate should have at least 3-8 years of hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments is required. Additionally, experience managing and customizing CDF files for parametric device libraries in Cadence is a must. Hands-on experience with the OpenAccess (OA) database API, familiarity with OA schema, and the ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data are essential. A deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks is also required. Experience in automating schematic and library processes using scripting languages (SKILL, Tcl, Python), solid knowledge of schematic editors/viewers, and maintaining schematic-layout synchronization are key skills for this role. Strong UNIX/Linux command-line skills and scripting abilities, experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent), excellent communication skills, and the ability to operate effectively in a startup team environment are crucial. Preferred qualifications include previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains, experience with Spectre, ADE simulation, and analog verification flows, understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design, and familiarity with AI/ML integration in design tools. If you are interested in this opportunity, please write to rekha.cxc@careerxperts.com to get connected!,

We are looking for a highly skilled EDA Engineer with expertise in Cadence Virtuoso environments and a strong understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. In this role, you will collaborate closely with AI/EDA development teams to establish seamless design flows and efficient automation for our AI-powered analog design platform. Your responsibilities will include developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. You will be tasked with creating, modifying, and optimizing SKILL scripts for automating layout, schematic, verification, and design environment tasks. Additionally, managing Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries will be a crucial part of your role. You will work extensively with the OpenAccess (OA) database API to read, write, and manipulate design data using languages like C++, Python, and Tcl. Developing automation tools and workflows leveraging OpenAccess, integrating foundry PDK/CDK devices, and troubleshooting issues related to PDK integration will be key responsibilities. Moreover, documenting technical processes, creating reusable scripts, and collaborating with AI and software teams for continuous improvement are essential aspects of this role. The ideal candidate should have at least 3-8 years of hands-on experience with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting, experience with OpenAccess database API, and a deep understanding of foundry PDK/CDK structures are required. Knowledge of schematic editors/viewers, UNIX/Linux command-line skills, and experience with version control systems in EDA environments are also necessary. Preferred qualifications include previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains, familiarity with Spectre, ADE simulation, and analog verification flows, as well as an understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. Experience with AI/ML integration in design tools would be a plus. If you believe you have the required skills and experience for this position, please write to rekha.cxc@careerxperts.com to get connected!,

YMTS INDIA is a premier software development company offering a wide range of software products, services, and solutions to various industries. With expertise in software development, mobile app development, web designing, web applications development, and embedded system integrated solutions, we excel in developing and maintaining software products, eCommerce portals, web applications, and embedded products. Additionally, we provide training and placement services. As an Analog Layout Designer at YMTS INDIA, you will be responsible for independently working on analog design at both block level and chip level based on schematics. This role requires hands-on experience in Analog Layout design of various designs such as SerDes, LVDS, DDR Phy, PLL, and Linear and Switching regulators. You will work at the transistor level and design Analog circuits in technologies with features of different nanometer technologies. Key Responsibilities: - Work independently on Analog design of block level and chip level from schematics. - Design Analog Layout of various designs including SerDes, LVDS, DDR Phy, PLL, and Linear and Switching regulators. - Design Analog circuits in technologies with features of different nanometer technologies. - Demonstrate a thorough working knowledge of layout design tool Cadence Virtuoso layout suite. - Possess strong knowledge of Analog electronics. - Understand issues involved in high-speed analog layouts. - Utilize skill scripting effectively. - Demonstrate good communication skills. - Show enthusiasm and self-motivation in working. - Deliver strong and effective presentations at multiple levels including senior management. Qualifications: - Education: B.E/B.Tech and M.E/M.Tech in Electronics and Communication Engineering. - Experience: Fresher/0-1 year. Job Types: Full-time, Permanent, Fresher Benefits: - Cell phone reimbursement - Yearly bonus Schedule: - Day shift - Fixed shift - Morning shift Education: Bachelor's (Preferred) Experience: Total work: 1 year (Preferred) Work Location: In person,

As an EDA Engineer, you will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Your role will involve creating, modifying, and optimizing SKILL scripts for automation of layout, schematic, verification, and design environment tasks. You will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Working extensively with the OpenAccess (OA) database API, using C++, Python, and Tcl, will be a key aspect of your responsibilities. You will be involved in reading, writing, and manipulating design data, including schematic, layout, connectivity, and library information. Developing automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist in design data migration or QA will also be part of your tasks. Troubleshooting issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups will be within your scope. Additionally, you will document technical processes, create reusable automation scripts, and contribute to team best practices. Collaboration with AI and software teams to integrate EDA tools into the AI co-pilot platform and support continuous improvement of design automation is essential. To succeed in this role, you should possess 3-8 years of hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments is required. Proven experience managing and customizing CDF files for parametric device libraries in Cadence is also important. Hands-on experience with the OpenAccess (OA) database API, familiarity with OA schema, and the ability to program in C++, Python, or Tcl for developing tools/scripts are necessary skills. A deep understanding of foundry PDK/CDK structures, experience automating schematic and library processes using scripting languages, solid knowledge of schematic editors/viewers, and maintaining schematic-layout synchronization are also vital for this role. Moreover, you should have strong UNIX/Linux command-line skills, experience with version control systems/tools used in EDA environments, excellent communication skills, and the ability to operate effectively in a startup team environment. Preferred qualifications include previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains, experience with Spectre, ADE simulation, analog verification flows, understanding of semiconductor process technology, and familiarity with AI/ML integration in design tools. For further information or to express interest in this position, please contact rekha.cxc@careerxperts.com.,

Your role will be to meet customers/prospects and identify qualify the opportunities, work out agreeable, equally importantly achievable, evaluation criteria, run through the evaluation and convert the opportunities into business and help customers to deploy the tool and get it running into production at the earliest. It requires a very good understanding of customer flow and a good analytical ability to resolve issues impacting production schedule. Hands-on knowledge of Advance Node layout and design rules would be a plus. The role demands a close interaction with RD and Product Engineering team for implementation of new features and bug fixes. As the job requires an extensive interaction with customers for issue resolution and identifying opportunities to proliferate Cadence technologies, at the same time a closer interaction with RD and other stakeholders, it demands an excellent customer and communication skills, and the leadership qualities. This position requires solid understanding of IC design technology and foundry process/methodology in analog layouts. It is essential to have a very good understanding of analog layout design fundamentals, advance node virtuoso techfile constraints and in-depth knowledge and hands-on experience on writing skill scripts to perform various layout automation tasks. The candidate should have knowledge of complete analog back-end flow from top level floorplanning down to complex block level layouts, physical verification, extraction, EMIR analysis etc, with proficiency in Cadence layout tools specifically Virtuoso with advance node exposure. Prior Design experience using Cadence CustomIC Physical Design tools (Virtuoso) and flows including chip integration and signoff is an added advantage. - B. Tech or equivalent with 3 to 5 years of relevant experience.

Job Title: Senior EDA Engineer - Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups. Document technical processes, create reusable automation scripts, and contribute to team best practices. Collaborate with AI and software teams to integrate EDA tools into Maieutics AI co-pilot platform and support continuous improvement of design automation. Required Skills & Experience: 3+ years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. Proven experience managing and customizing CDF files for parametric device libraries in Cadence. Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). Strong UNIX/Linux command-line skills and scripting abilities. Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). Excellent communication skills and ability to operate effectively in a startup team environment. Preferred Qualifications: Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains. Experience with Spectre, ADE simulation, and analog verification flows. Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. Familiarity with AI/ML integration in design tools is a plus.

Job Title: Senior EDA Engineer Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. Troubleshoot issues related to PDK integration, OA database consistency, schematic layout synchronization, and environment setups. Document technical processes, create reusable automation scripts, and contribute to team best practices. Collaborate with AI and software teams to integrate EDA tools into our AI co pilot platform and support continuous improvement of design automation. Required Skills & Experience: 3–8 years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. Proven experience managing and customizing CDF files for parametric device libraries in Cadence. Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). Strong UNIX/Linux command-line skills and scripting abilities. Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). Excellent communication skills and ability to operate effectively in a startup team environment. Preferred Qualifications: Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains. Experience with Spectre, ADE simulation, and analog verification flows. Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. Familiarity with AI/ML integration in design tools is a plus.