Product Validation Engineer II Cadence Design Systems

2.0 - 6.0 years

0 Lacs

noida, uttar pradesh

On-site

At Cadence, you have the opportunity to join the Modus R&D team as a DFT Product Validation Engineer. Your role will involve validating and supporting Design-for-test (DFT) technologies with a focus on insertion and validation of various DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST, etc. You will utilize Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on both in-house and customer designs. Your expertise in DFT/ATPG/ASIC Design flows, RTL Verilog/VHDL coding styles, and Synthesis will be essential in this role. Key Responsibilities: - Validate and support DFT technologies using Cadence tools - Create testplans f...

Posted 1 week ago

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Product Validation Engineer II Cadence

2.0 - 6.0 years

0 Lacs

noida, uttar pradesh

On-site

As a Product Validation Engineer at Cadence Design Systems, you will be a crucial part of the Modus R&D team, focusing on validating and supporting Design-for-test (DFT) technologies. Your role will involve working on complex problems that require innovative thinking, debugging customer reported issues, and collaborating with R&D to provide out-of-box solutions with an emphasis on robustness, PPA, and scalability. **Key Responsibilities:** - Work on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST, etc., using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer design...

Posted 1 week ago

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Product Validation Engineer II Cadence Design Systems

2.0 - 6.0 years

0 Lacs

noida, uttar pradesh

On-site

At Cadence, we are constantly seeking talented and motivated individuals to join our team and contribute to the ever-evolving world of technology. As part of the Modus R&D team at Cadence Design Systems, we are currently looking for an engineer who is passionate about validating and supporting Design-for-test (DFT) technologies. The ideal candidate should have a minimum of 2 years of experience in DFT/ATPG/ASIC Design flows, along with a solid understanding of RTL Verilog/VHDL coding styles and Synthesis. In this role, you will be responsible for working on complex problems that require innovative thinking and collaborating with various teams to propose out-of-box solutions focusing on robus...

Posted 2 months ago

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