RTL Micro-Architecture Design Engineer DRAM Controller

As a VLSI RTL IP or Subsystem designer with 5 to 14 years of experience, you will be responsible for designing and developing CXL and DRAM controller (DDR4/5) based intellectual property. Your role will involve engaging with other architects within the IP level to drive Micro-Architectural definition and delivering quality micro-architectural level documentation. You will need to produce quality RTL on schedule by meeting PPA goals and be accountable for logic design/RTL coding, RTL integration, and timing closure of blocks. Collaboration with the verification team will be essential to ensure implementation meets architectural intent. Your hands-on experience in running quality checks such as Lint, CDC, and Constraint development will be valuable, along with a deep understanding of fundamental concepts of digital design. Key Responsibilities: - Design and develop CXL and DRAM controller based intellectual property - Engage with other architects to define Micro-Architecture - Deliver quality micro-architectural level documentation - Produce quality RTL on schedule meeting PPA goals - Responsible for logic design/RTL coding, integration, and timing closure - Collaborate with verification team to ensure implementation meets architectural intent - Conduct quality checks such as Lint, CDC, and Constraint development - Debug designs in simulation environments - Have a deep understanding of fundamental concepts of digital design Preferred Skills: - Strong Verilog/System Verilog RTL coding skills - Experience with DRAM Memory Controller design - Knowledge of DRAM standard (DDR4/5) memory - Interface/Protocol experience required: AHB/AXI, Processor local bus, Flash, SPI, UART, etc. - Experience with Xilinx/Intel FPGA Tool flow - Knowledge of PCIe/PIPE - Knowledge of projects with Microblaze, ARM cores, etc. - Appreciation for CXL Protocol Qualifications Required: - Masters degree or Bachelors degree in Electronics or Electrical Engineering - 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure (Note: Additional details about the company were not included in the provided job description.),