RTL Design Engineer

Role Overview: You will play a crucial role in shaping the future of hardware experiences as a part of the team working on custom silicon solutions for Google's direct-to-consumer products. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services, aiming to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Key Responsibilities: - Collaborate with architects to develop microarchitecture - Perform Verilog/SystemVerilog RTL coding - Conduct functional/performance simulation debugging - Conduct Lint/CDC/FV/UPF checks - Participate in test planning and coverage analysis - Develop RTL implementations meeting power, performance, and area goals - Be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up - Create tools/scripts to automate tasks - Track progress and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains Qualifications Required: - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience - At least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog - Experience in the design and development of Security or Audio blocks - Experience with a scripting language like Perl or Python - Familiarity with DSI2 or MIPI C/D Phy - Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science (ideally) - Experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT (preferred) - Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture (beneficial),