2 Parameterized Cells Jobs

As an EDA Engineer, you will be responsible for developing, maintaining, and optimizing analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Your role will involve creating, modifying, and optimizing SKILL scripts for automation of layout, schematic, verification, and design environment tasks. You will manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Working extensively with the OpenAccess (OA) database API, using C++, Python, and Tcl, will be a key aspect of your responsibilities. You will be involved in reading, writing, and manipulating design data, including schematic, layout, connectivity, and library information. Developing automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist in design data migration or QA will also be part of your tasks. Troubleshooting issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups will be within your scope. Additionally, you will document technical processes, create reusable automation scripts, and contribute to team best practices. Collaboration with AI and software teams to integrate EDA tools into the AI co-pilot platform and support continuous improvement of design automation is essential. To succeed in this role, you should possess 3-8 years of hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments is required. Proven experience managing and customizing CDF files for parametric device libraries in Cadence is also important. Hands-on experience with the OpenAccess (OA) database API, familiarity with OA schema, and the ability to program in C++, Python, or Tcl for developing tools/scripts are necessary skills. A deep understanding of foundry PDK/CDK structures, experience automating schematic and library processes using scripting languages, solid knowledge of schematic editors/viewers, and maintaining schematic-layout synchronization are also vital for this role. Moreover, you should have strong UNIX/Linux command-line skills, experience with version control systems/tools used in EDA environments, excellent communication skills, and the ability to operate effectively in a startup team environment. Preferred qualifications include previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains, experience with Spectre, ADE simulation, analog verification flows, understanding of semiconductor process technology, and familiarity with AI/ML integration in design tools. For further information or to express interest in this position, please contact rekha.cxc@careerxperts.com.,

Job Title: Senior EDA Engineer - Cadence Virtuoso, SKILL/CDF, Tool Integration Role Overview: We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. This role will collaborate closely with AI/EDA development teams to build seamless design flows and robust automation for our AI-powered analog design platform. Key Responsibilities: Develop, maintain, and optimize analog/mixed-signal IC design flows in Cadence Virtuoso and related EDA tools. Create, modify, and optimize SKILL scripts for automation of layout, schematic, verification, and design environment tasks. Manage Component Description Format (CDF) parameters and configurations for foundry PDK and CDK components/libraries. Work extensively with the OpenAccess (OA) database API (using C++, Python, Tcl) to read, write, and manipulate design data including schematic, layout, connectivity, and library information. Develop automation tools and workflows leveraging OpenAccess to integrate schematic and layout views, support PDK/CDK validation, and assist design data migration or QA. Integrate and validate foundry PDK/CDK devices, parameterized cells (pCells), symbols, DRC/LVS decks, and simulation models with EDA tools. Troubleshoot issues related to PDK integration, OA database consistency, schematic-layout synchronization, and environment setups. Document technical processes, create reusable automation scripts, and contribute to team best practices. Collaborate with AI and software teams to integrate EDA tools into Maieutics AI co-pilot platform and support continuous improvement of design automation. Required Skills & Experience: 3+ years hands-on experience working with Cadence Virtuoso analog/mixed-signal design flows. Strong proficiency in SKILL scripting for automation within Cadence layout and schematic environments. Proven experience managing and customizing CDF files for parametric device libraries in Cadence. Hands-on experience with OpenAccess (OA) database API: Familiarity with OA schema, ability to program in C++, Python, or Tcl to develop tools/scripts that access and modify OA layout and schematic data. Deep understanding of foundry PDK/CDK structures, including parameterized cells, symbols, device models, layout generators, and associated design-rule decks. Experience automating schematic and library processes using scripting languages (SKILL, Tcl, Python). Solid knowledge of schematic editors/viewers and maintaining schematic-layout synchronization (LVS/Schematic Driven Layout). Strong UNIX/Linux command-line skills and scripting abilities. Experience with version control systems/tools used in EDA environments (Git, SOS, or equivalent). Excellent communication skills and ability to operate effectively in a startup team environment. Preferred Qualifications: Previous work experience at Cadence or semiconductor companies specializing in Virtuoso toolchains. Experience with Spectre, ADE simulation, and analog verification flows. Understanding of semiconductor process technology and device physics applicable to analog/mixed-signal design. Familiarity with AI/ML integration in design tools is a plus.