Ams Verification Engineer Coventine Digital

5.0 - 10.0 years

12 - 20 Lacs

Bengaluru

Hybrid

Key Responsibilities: Lead verification of analog and mixed-signal IP blocks including: Bandgaps, LDOs, Buck (multi-phase) switching regulators Comparators and Functional Safety (FuSa) monitoring circuits Own and execute block-level verification plans with comprehensive coverage. Develop and maintain analog behavioral models using SystemVerilog Real Number Modeling (SV-RNM) . Verify embedded digital functionalities such as: CRC, Clock Monitoring, OTPs, Register Maps Communication Interfaces (e.g., SPI, IC) Write and implement SystemVerilog assertions and covergroups . Perform advanced debug at both RTL and schematic levels. Manage VSIF files and support regression execution. Perform coverage analysis using tools like IMC or vManager . (Bonus) Scripting using Makefiles or automation tools.

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AMS Verification Engineer Coventine Digital

5.0 - 10.0 years

6 - 15 Lacs

Pune, Bengaluru

Work from Office

Key Responsibilities: Develop AMS verification environments from the ground up using SystemVerilog/UVM Own and execute test planning, AMS setup, and mixed-signal simulation Work on SerDes verification involving high-speed protocols (PCIe, USB 3.0, MIPI, etc.) Model and verify analog/mixed-signal blocks using wreal , RNM , and Verilog-A Perform simulations using VCS Primesim AMS and Primesim XA tools Collaborate closely with analog, digital, and system teams for integrated AMS verification

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