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3.0 - 6.0 years
3 - 6 Lacs
Hyderabad / Secunderabad, Telangana, Telangana, India
On-site
Create comprehensive test plans and verification strategies aligned with specifications Develop modular and reusable testbenches using SystemVerilog Write both directed and random tests to validate functionality Perform functional and code coverage modeling, analysis, and reviews Debug mismatches between RTL design and C-model behavior Integrate internal and third-party verification IP for full-chip simulations Review and optimize existing test suites and verification environments Mentor junior engineers and assist in skill development Ensure test plans are fully traceable to design specifications using coverage databases The Impact You Will Have: Lead innovation in processor and IP verifica...
Posted 4 months ago
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