6 Memory Layout Jobs

Alternate Job Titles: Memory Design Engineer CMOS Memory R&D Engineer Embedded Memory Engineer Analog Circuit Engineer ASIC Memory Design Associate We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusiastic engineer who is passionate about memory design and eager to contribute to next-generation semiconductor technologies. With a strong academic foundation in Electrical Engineering, Telecommunication, or related fields, you thrive in dynamic environments and excel at tackling complex technical challenges. You bring a curiosity-driven mindset and a commitment to continuous learning, always seeking to expand your knowledge and stay ahead of industry trends. Your attention to detail ensures robust and reliable designs, while your analytical skills enable you to solve problems efficiently and innovatively. You are self-motivated, organized, and take pride in delivering high-quality resultswhether working independently or as part of a collaborative team. Communication comes naturally to you, allowing you to articulate ideas clearly and build strong relationships with colleagues across functions. You value diversity and inclusion, understanding the importance of varied perspectives in driving creative solutions. You are future-focused, driven to make a meaningful impact and eager to grow your career in a supportive, world-class environment. What Youll Be Doing: Designing and developing CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM for advanced applications. Architecting and implementing high-speed, low-power, and high-density memory solutions with rigorous attention to performance and efficiency. Performing schematic entry, circuit simulation, and comprehensive design verification and validation. Developing and verifying bit cells, ensuring robust and reliable memory operation. Collaborating with cross-functional teams to troubleshoot design issues and optimize layouts using industry-standard tools. Managing your own workflow and contributing to project planning, leveraging autonomy to deliver on key milestones. Providing technical support and participating in additional duties as required to advance project goals. The Impact You Will Have: Enable the development of cutting-edge silicon chips that power next-generation devices and systems. Drive innovation in memory design, contributing to higher performance, lower power consumption, and increased chip density. Help Synopsys maintain its leadership in the semiconductor industry by delivering reliable, high-quality IP solutions. Support the advancement of pervasive intelligence technologies, from AI-driven applications to automotive safety systems. Collaborate in a global, diverse team, fostering a culture of inclusion and continuous improvement. Champion best practices in design verification, ensuring robust products and satisfied customers. What Youll Need: Bachelors or Masters degree in Electrical Engineering, Telecommunication, or a related field. 0-2 years of hands-on experience in memory design, preferably with CMOS technologies. Proficiency in CMOS memory design, circuit simulation, memory layout, and layout verification/debugging tools. Programming skills in C-Shell, Perl; experience with C++ or JavaScript is a plus. Excellent analytical and problem-solving abilities, with a detail-oriented approach. Who You Are: Self-motivated, self-directed, and highly organized. Strong interpersonal and teamwork skills, with effective communication in English (verbal and written). Professional, future-oriented, and committed to continuous learning. Critical and logical thinker, able to negotiate and resolve challenges efficiently. Inclusive and respectful of diverse perspectives, fostering collaboration and innovation. The Team Youll Be A Part Of: You will join a dynamic and collaborative R&D engineering team in Bangalore focused on embedded memory design. Our team is committed to pushing technological boundaries, fostering knowledge sharing, and supporting individual growth. Together, we drive the development of high-performance, energy-efficient memory solutions that form the backbone of Synopsys world-leading IP portfolio. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are looking for a Senior Digital/Memory Mask Design Engineer someone who is excited to join a growing group of diverse individuals responsible for handling challenging high-speed digital memory circuit designs. What You'll Be Doing Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm, and lower nodes following industry standard methodologies. Deliver layouts for Full Custom Memory group specializing in digital Memory circuits. IP layout will comprise of significant digital components. Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts. Follow company procedures and practices for IC layout activities. What We Need To See B.E/B Tech. / M Tech in Electronics or equivalent experience with 5+ Years of proven experience in Memory layout in advanced CMOS process. Detailed knowledge of industry standard EDA tools for Cadence. Experience with layout of high-performance memories of various types. Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding). Experience with floor planning, block level routing and macro level assembly. Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc. We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

Role & responsibilities JD: Advanced memory layout design (SRAM, ROM, custom) Hands-on with FinFET, Virtuoso, Calibre, PVS Tight collaboration with circuit & verification teams Mastery in DRC/LVS, parasitic optimization, and layout efficiency Experience with foundry tech files and tapeout is a huge plus!

The role requires 3 to 8 years of experience in SRAM Memories layout design. You should be well-versed in various levels of memory layouts including custom memory bits, leaf cells, control blocks, Read-Write, Sense Amplifiers, and decoders. Proficiency in floor planning, power planning, block area estimation of memory designs or compliers is essential. You must have expertise in leaf cell layout development and physical verification. Additionally, a good understanding of schematics, interface with circuit designer and CAD, and process development team is required. Strong knowledge of layout fundamentals such as Electro-migration, Latch-up, coupling, crosstalk, IR-drop, parasitic analysis, matching, shielding, etc. is necessary. Understanding layout effects on the circuit like speed, capacitance, power, and area is crucial. Excellent problem-solving skills in solving area, power, performance, and physical verification of custom layout are expected. Experience with Cadence tools including Virtuoso schematic editor, Virtuoso layout L, XL & Verification tools like Mentor Calibre is preferred. Leadership qualities and the ability to multitask are important. Working in a team environment, guiding, and providing technical support to team members are key responsibilities. Self-motivation, hard work, goal orientation, and excellent verbal and written communication skills are essential. Knowledge of Skill coding and layout automation is a plus. Responsibilities include Memory Compiler layout development and verification, Layout design and development of Memory blocks such as Array, Row/Column decoder, sense amplifier, pre-charge, Control blocks for SRAM. Performing layout verification like LVS/DRC/Latchup, quality check, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedule/milestones in a multiple project environment. Guiding junior team-members in their execution of Sub block-level layouts & reviewing their work. Contributing to effective project management and effectively communicating with engineering teams to assure project success. UST is a global digital transformation solutions provider that has been operating for over 20 years. UST partners with clients from design to operation, embedding innovation and agility into their organizations. With over 30,000 employees in 30 countries, UST aims to make a boundless impact touching billions of lives in the process.,

Role & responsibilities: Outline the day-to-day responsibilities for this role. Preferred candidate profile: Specify required role expertise, previous job experience, or relevant certifications.

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow