3 Memory Consistency Jobs

Are you interested in working with a world-class CPU design team at Qualcomm India Private Limited Do you have a passion for applying formal methods to verify application processors and contributing to the development of next-generation formal methodologies Qualcomm's CPU team is at the forefront of developing processors that will power the future. Join us on this exciting adventure and maximize your formal verification skills on complex designs. As a member of the CPU design team, you will collaborate closely with the design team to grasp design intent and establish verification plans with a focus on end-to-end formalization from architecture to micro-architecture refinement. Your responsibilities will include defining formal verification architecture, creating test plans, and constructing formal sign-off environments for Qualcomm CPU components. You will deploy model-checking technology across hardware designs, encompassing property verification, mathematical proofs, architectural modeling, and validation in cutting-edge application areas. To excel in this role, you should hold a BA/BS degree in CS/EE with over 8 years of practical experience in applying formal methods in hardware or software. A solid background in model checking or theorem proving for complex systems is essential. Proficiency in writing assertions, developing modeling code in Hardware Description Languages, or ensuring correctness of architectural specifications using formal methods is required. Familiarity with model checkers like Jaspergold and VC-Formal, or theorem-proving tools such as ACL2 and HOL, is advantageous. The ideal candidate would possess an MS/PhD degree in CS/EE with at least 4 years of practical experience and a strong foundation in formal methods applied to hardware specifications or implementations. Domain knowledge in areas such as microprocessor architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, and security architectures is beneficial. Additionally, strong software engineering skills, automation abilities, and proficiency in programming languages like C++, Python, or TCL are preferred. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 4+ years of Hardware Engineering experience OR - Master's degree in Computer Science, Electrical/Electronics Engineering, or related field with 3+ years of Hardware Engineering experience OR - PhD in Computer Science, Electrical/Electronics Engineering, or related field with 2+ years of Hardware Engineering experience Qualcomm is an equal opportunity employer that provides accommodations for individuals with disabilities during the application and hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. Qualcomm expects employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. For further information about this role, please reach out to Qualcomm Careers.,

Your role and responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Introduction As a Hardware at , youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.