4 Dft Implementation Jobs

You will be responsible for driving DFT implementation in Wireless SoC chips. You will have full ownership of ATPG architecture, design, implementation, verification, and deployment to Silicon testing, collaborating with Test engineers. Your duties will also involve MBIST design, implementation, and verification for all memories in the SoC. You should be capable of generating and debugging DFT patterns on the tester. You will work closely with the design, design-verification, and backend teams to facilitate the integration and validation of the test logic in all phases of the design and backend implementation flow. To excel in this role, you are required to have 8-10 years of experience and a B.Tech/M.Tech degree in ECE or EEE. You must possess full-chip DFT working experience with multiple design Tape Outs and expert knowledge of DFT architecture on complex Designs with multiple clock domains. Furthermore, experience in ATPG for pattern generation and simulation of Test Transition faults, Stuck-at, IDDQ, at-speed faults is essential. Hands-on experience in industry-standard DFT tools like Mentor Tessent suite or Synopsys DFT compiler is also a must-have. Your responsibilities will also include block-level and chip-level SCAN insertion, DRC, Coverage Analysis, and improvements. Expertise in Scan Compression (EDT/OPMISR+), MBIST, ATPG implementation, and verification is crucial. You should have expert knowledge of Test time reduction, good knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments & LEC. Developing/automating flows and scripts in Perl/Tcl to enhance the DFT methodologies & process is expected from you. Experience working with cross-functional global teams, Low-Power DFT requirements, and Low-Power MBIST architectures and Memory testing is also necessary. Preferred qualifications include experience in DFT related RTL integration, excellent communication and analytical skills, experience in leading junior teams, mentoring/training, and project leadership, as well as exceptional problem-solving skills. In addition to the challenging work environment, you can look forward to benefits such as Equity Rewards (RSUs), Employee Stock Purchase Plan (ESPP), insurance plans with Outpatient cover, National Pension Scheme (NPS), flexible work policy, and childcare support. Join us and be a part of a highly skilled team where every engineer's contribution significantly impacts the product, while also enjoying a good work/life balance and a welcoming and fun work environment.,

As part of the ASIC modeling team, you will be responsible for developing, maintaining, and testing the NAND/SoC models using C/C++/SystemC. The SoC models aim to accurately capture the functionality of the controller chip that oversees the NAND storage. You should have 4 to 7 years of experience and possess expertise in DFT implementation and verification. Additionally, experience in MBIST implementation and verification, along with a strong grasp of DFT/MBIST fundamentals, is essential. You will be involved in tasks such as DRC Clean up, coverage improvement, and modifying MBIST algorithms. It would be beneficial to have knowledge in PERL/TCL Scripting/Python and using assertions for monitoring clock frequencies and test-related registers. Familiarity with yield analysis and improvement flow, understanding CLP constructs, and working in multi-voltage, multi-power design environments will be advantageous. Your expected roles will include architecting DFT based on the PETE, Design, and Customer specifications. A self-motivated, self-driven attitude with a thirst for learning is desirable for this position. The ideal candidate should hold a BE/Btech/Mtech/ME degree. Western Digital values diversity and believes that embracing various perspectives leads to the best outcomes. The company is dedicated to creating an inclusive environment where every individual can thrive through a sense of belonging, respect, and contribution. Western Digital is committed to providing equal opportunities to applicants with disabilities. If you require accommodations during the application process, please contact us at staffingsupport@wdc.com with details of your request, including the job title and requisition number.,

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Requirements: 8+ years of experience in DFT implementation and verification Hands-on experience with tools like Tetramax, TestMax, Fastscan, or MBISTArchitect Strong understanding of scan/ATPG, JTAG, BIST, and IEEE 1149.x standards Experience in silicon bring-up, failure analysis, and debug Familiarity with industry-standard flows and ATE constraints Excellent problem-solving and team collaboration skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of DFT.

Lead the deployment of Synopsys DFT technologies across key customer projects Act as the primary point of contact, facilitating smooth communication with customers and internal teams Define and manage project schedules, tracking milestones, and deliverables Identify potential risks early, escalate issues as needed, and ensure timely resolutions Ensure projects meet schedule, quality, and customer satisfaction benchmarks Collaborate with AE and R&D teams to meet technical and functional objectives Manage multiple project executions, ensuring seamless alignment with business goals Prepare and deliver progress updates and technical presentations to stakeholders The Impact You Will Have: Guarantee effective adoption of Synopsys DFT solutions in high-impact customer designs Enhance cross-functional team collaboration and ensure project alignment with business needs Contribute to Synopsys leadership in DFT implementation through timely and quality project deliveries Boost customer success and satisfaction with streamlined communication and delivery Proactively mitigate project risks, ensuring strong project health and stakeholder confidence What You'll Need: 510 years of experience with hands-on implementation of DFT technologies Strong expertise in Scan Compression, ATPG, LogicBIST, MemoryBIST, Boundary Scan Proven ability to manage multiple projects and deliver results under tight schedules Excellent communication, leadership, and organizational skills Proficiency in Microsoft Office tools (PowerPoint, Excel, Word) for documentation and reporting