Design Verification Engineer ACL Digital

3.0 - 5.0 years

0 Lacs

bengaluru, karnataka, india

On-site

Design Verification Experience : 3-5 years Location : Bangalore Following skill set is required: Candidate must have GLS hands on experience in ZD/PAGLS/SDF/Scan dump verification. Strong Debug, UVM, System Verilog and Digital Fundamentals Should be able to debug Netlist functional failure. Low Power Awar verification. Timing Simulation failure, setup and hold violation fundamentals. Scan dump verification. Understanding Specs and Standards and developing relevant test plans. Monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved. Good understanding of DDR families (LP/PC) and g...

Posted 1 week ago

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ASIC/RTL Design Engineer(DDR)- Staff Qualcomm

2.0 - 7.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Mult...

Posted 1 month ago

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