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4.0 - 8.0 years
9 - 13 Lacs
hyderabad, bengaluru
Work from Office
Location : Bangalore / Hyderabad Job Description: TSMC 16/12nm,7nm,5nm,3nm and below (other foundries are also fine like Intel, Samsung, GF). Preferably TSMC 5nm/3nm experience. Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Verification flows LVS/DRC/DFM/Antenna check/EMIR experience. Responsible for on-time delivery of block-level layouts of acceptable quality. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. BE or MTech in Electronics/VLSI Engineering Good communications skills as we work with cross-functional teams. Share the profiles who have good hands-on experience in rece...
Posted 3 days ago
3.0 - 7.0 years
7 - 12 Lacs
bengaluru
Work from Office
1. Design and development of key full custom analog blocks/sub blocks for Tx /Rx/PLL/CLK Distribution modules for 32G/50G/112G IO links and general purpose IO transceiver macros for PCIe, optical IO interfaces using industry's latest 7nm / 14nm FinFet technology. 2. Complete ownership of analog macro development starting from - understanding data sheet specifications, - driving/creating design specifications for macros, - defining architecture, - design analog sub blocks/modules, - creating simulation plan and execute, - developing floorplan for macro, - working closely with layout engineers for layout, - good understanding of EM/IR/Self heating issues and mitigation - understanding layout e...
Posted 1 week ago
8.0 - 12.0 years
0 Lacs
bengaluru, karnataka, india
On-site
L&T Technologies is looking to hire for SOC DV Lead role. Job Location : Bangalore Job Title : SoC DV Lead YEARS OF EXPERIENCE : 8+ Years JOB DESCRIPTION: Expertise in verifying SOC based on ARM and RISC CPU's. Define and implement ASIC / SoC verification plans, and build verification test benches to enable ASIC, sub-system, SoC level verification. Develop functional tests based on a verification test plan. 8 to 12+ Years of experience in DV 3 to 6+ years of experience in AMS Verification is a must Experience in Co simulation (RTL + Spice) Good understanding on Analog blocks Experience in System Verilog, UVM is must Experience in WREAL, RNM, Vams modelling is a plus
Posted 1 week ago
3.0 - 8.0 years
15 - 27 Lacs
bengaluru
Work from Office
Role & responsibilities Description : 4 to 8 years of experience in Design and development of critical analog, mixed-signal, custom digital block. TSMC 16/12nm,7nm,5nm,3nm and below (foundries are also fine like Intel, Samsung, GF) Preferably TSMC 5nm/3nm experience. Responsible full chip level integration support. Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience. Responsible for on-time delivery of block-level layouts of acceptable quality. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Analog blocks like Regulators/Charge pumps/Power Management etc.. HBM experience is an added advantage. PLs share resumes/CV to pradeep.b@acesoftlabs.com Preferred c...
Posted 2 months ago
3.0 - 8.0 years
10 - 20 Lacs
hyderabad
Work from Office
Role & responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Excellent problem-solving skills in physical verification of custom layout. Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. Ability to guide junior team-members in their execution of Sub block-level layouts & review critical...
Posted 2 months ago
3.0 - 8.0 years
25 - 40 Lacs
hyderabad
Work from Office
BE/B.Tech in ECE /M.Tech in VLSI with 3 to 9 years experience in Analog Mixed Signal Verification Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks Very Good experience in Analog Mixed Signal verification simulation tools. Good experience in System Verilog, UVM methodologies Able to train the team members and guide them to the solutions for problems Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. Good experience in Gate level netlist simulation Experience in Python, Perl, Shell scripting is added advantage. Good communication and documentation skills
Posted 2 months ago
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